MB81P643287 Datasheet, PDF (41/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
Fig. 12 - AC TIMING, PULSE WIDTH
CLK
VX
VX
CLK
IRAS, IRP, IRPA, IRCD, IRRD, tREF, tAREF
Input
(Controls &
Command
Command
Addresses)
Note: All parameters listed above are measured from the cross point at rising edge of the CLK and
falling edge of CLK of one command input to next command input.
CKE
CLK
CLK
Fig. 13 - AC TIMING of Precharge Power Down Mode
IRC (Min.), tREF (Max.)
VREF
tIS
tPDEX
IPDEXP (Min.) *2
ICKE
Note*1
Command
NOP
NOP
NOP
Don't Care
NOP
NOP
ACTV
Notes: *1. Minimum 2 clock cycles is required for complete power down on clock buffer.
*2. If either any supply voltage or clock input condition is changed from the previous operating
condition (other than PDEN and REF), lSCD must be satisfied prior to any command input.
CKE
CLK
CLK
Fig. 14 - AC TIMING of Self-refresh Mode
IRFC (Min.) *²
VREF
tIS
tPDEX
ISCD *³ or IXSNR
ICKE
Note *¹
Command
NOP
SELF
NOP
Don't Care
NOP
NOP
ACTV
Notes: *1. Minimum 2 clock cycles is required for complete power down on clock buffer.
*2. CKE must maintain High level and clock must be provided during the lSCD period. lSCD must
be satisfied before read command input.
*3. lSCD must be satisfied before read command input.
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