MB81P643287 Datasheet, PDF (44/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAM - 4: WRITE (EXAMPLE @ BL = 4)
CLK
CLK
CKE _High
Command
DQS (Input)
ICCD (Min.)
WRIT
WRIT
Don't Care
tDSPRES tDSPREH _tDQSS
tDSPRE
tDQSS
NOP
Don't Care
Don't Care
DQ0 to DQ31
(Input)
Don't Care
D1 D2 D1 D2 D3 D4
Note: DQS Setup Time, tDQSS, must be within a range of 0.75*tCK to 1.25*tCK from write command Input.
TIMING DIAGRAM - 5: DM, WRITE DATA MASK (EXAMPLE @ BL = 4)
CLK
CLK
Command
DQS (Input)
WRIT
NOP
tDQSS
Don't Care
WRIT
tDQSS
NOP
Don't Care
DM
DQ0 to DQ31
(Input)
Don't Care
Don't Care
lDQD = 0
lDQD = 0
D1 D2  D4
Masked
D1  D3 D4
Masked
Don't Care
Don't Care
Note: DM are latched by DQS Input together with Data Input after write command.
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