MB81P643287 Datasheet, PDF (26/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
Fig. 3 - SDRAM READ TIMING EXAMPLE (@ CL=2 & BL=2)
<SDRAM>
t0
t1
t2
t3
t4
CLK
(external)
Command
DATA
READ
Stored by CLK input
Hi-Z
Q1
Q2
Output in every rising CLK edge
< DDR SDRAM >
CLK
CLK
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
Command
DQS
DATA
READ
Stored by CLK input
Hi-Z
Low
Hi-Z
High
DQS signal transition
occurs at the same
time as data bus.
Q1
Q2
Output in every
cross point of clock input
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