MB81P643287 Datasheet, PDF (29/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
Notes: *1. VREF is expected to track variations in the DC level of VDDQ of the transmitting device. Peak-to-Peak
noise level on VREF may not exceed ± 2% of the supplied DC value.
*2. VTT is used for SSTL_2 bus and is not applied to the device. VTT is expected to be set equal to VREF
and must be track variations in the DC level of VREF.
*3. Applicable when signal(s) is terminated to the VTT of SSTL_2 bus.
*4. VISO means {VIN(CLK) + VIN(CLK)} / 2. Refer to Differential Input Signal Definition.
*5. Overshoot limit: VIH (Max.) = VDD + 1.0V for pulse width ≤ 4 ns acceptable, pulse width measured at
50% of pulse amplitude.
*6. Undershoot limit: VIL (Min.) = VSS -1.0V for pulse width ≤ 4 ns acceptable, pulse width measured at
50%of pulse amplitude.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Differential Input Signal Definition
Fig. 4 - Differential Input Signal Offset Voltage (For Clock Input)
CLK
CLK
VSS
IVSWINGI
0 V Differential
VISO
VSS
VISO (Min.)
VX
VSWING (AC)
VISO (Max.)
s CAPACITANCE
Parameter
Input Capacitance, Address & Control
Input Capacitance, CLK & CLK
Input Capacitance, DM0 to DM3
I/O Capacitance
Symbol
CIN1
CIN2
CIN3
CI/O
Min.
2.5
2.5
4.0
4.0
Typ.
—
—
—
—
(TA = 25°C, f = 1 MHz)
Max.
Unit
3.5
pF
3.5
pF
5.5
pF
5.5
pF
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