MB81P643287 Datasheet, PDF (57/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAMS
TIMING DIAGRAM - 1: POWER-UP TIMING DIAGRAM
VDD
100 µs Pause Time
Test Mode Entry Point
CS
CKE
CAS
*1
CLK
*3
tETD
CLK
or
CLK
CLK
*2
Notes: *1. CAS shall be staid either High or Low at power on.
*2 . All output buffers maintains in High-Z state regardless of the state of control signals except
for CAS as long as the above timing is maintained.
*3. CAS must not be brought from High to Low.
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