MB81P643287 Datasheet, PDF (40/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
Fig. 9 - AC TIMING of Read Mode (Clock to DQS Output Delay Time)
CLK
CLK
tQSLZ
(Min.)
DQS Output VTT
(@BL = 4)
VTT − 0.2 V
tCK
tCK
tQSCK(Min.)
tQSPRE
tQSCK
(Min.)
tQSCK
(Max.)
tQSCK
(Min.)
tQSCK
(Max.)
tQSCK
(Min.)
tQSCK
(Max.)
VX
tQSHZ
tQSCK
(Max.)
tQSV
tQSV
tQSV
tQSPST
Note: DQS Access time (tQSCK) is measured from the cross point of clock (VX) and VREF.
The end of tQSPST and tQSHZ specification is defined at where output buffer is no longer driven.
CLK
CLK
DQS Data
Output
(@BL = 4)
Fig. 10 - AC TIMING of Read Mode (Clock to Data Output Delay Time)
tCK
tCK
VTT
tLZ
(Min.)
VTT + 0.2 V
VTT − 0.2 V
tACC
(Min.)
tACC
(Max.)
tACC
(Min.)
tACC
(Max.)
tACC
(Min.)
tACC
(Max.)
VX
tHZ
tACC
(Max.)
Note: Access time (tACC) is measured from the cross point of clock (VX) and VREF.
The end of tHZ specification is defined at where output buffer is no longer driven.
Fig. 11 - AC TIMING of Read Mode (DQS Output to Data Output Delay Time)
DQS Output
(@BL = 4)
DQ Data
VTT
Output
(@BL = 4)
tQSQ
(Min.)
VTT + 0.2 V
VTT − 0.2 V
tQSQ
(Min.)
tQSQ
(Max.)
tDV
tQSQ
(Min.)
tQSQ
(Max.)
tDV
tQSQ
(Min.)
tQSQ
(Max.)
VREF
tQSQ
(Max.)
tDV
tDV
Note: DQS Output Edge to Data Output Edge Skew Time (tQSQ) is measured from VTT to VTT.
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