MB81P643287 Datasheet, PDF (45/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAM - 6: READ WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2.0, BL = 4 Applied to same bank)
CLK
CLK
IRAS (Min.)
BL _{× tCK + lRP (See note)}
2
IRP (Min.)
Command
ACTV
Hi-Z
DQS (Output)
READA
IRCD (Min.)
CAS Latency
ACTV
DQ0 to DQ31 ^Hi-Z
(Output)
Q1 Q2 Q3 Q4
Note: Internal precharge operation at Read with Auto-precharge command (READA) is started BL/2
clock later from READA command.
If BL=2, the READA command should not be issued no earlier than 1 clock (BL/2 = 1) before
lRAS (Min.).
If BL=4, the READA command should not be issued no earlier than 2 clock (BL/2=2) before lRAS
(Min.).
TIMING DIAGRAM - 7: WRITE WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2.0, BL = 4 Applied to same bank)
CLK
CLK
IWAL (Min.)
IRAS (Min.) (See note)
Command
ACTV
Hi-Z
DQS (Input)
WRITA
IRCD (Min.)
tDQSS
ACTV
DQ0 to DQ31 ^Hi-Z
(Input)
D1 D2 D3 D4
Note: Write with Auto-precharge command (WRITA) must be issued after lRCD is satisfied and be
considered to meet lRAS requirement applied to end of burst length (BL) regardless of where it is
masked or not.
45