MB81P643287 Datasheet, PDF (31/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
(Continued)
Parameter
Symbol
Condition
Value
Unit
Min. Max.
Burst Read Current
(Average Power
Supply Current)
MB81P643287-50
MB81P643287-60
IDD4R
Burst Length = 4,
CAS Latency = 3,
All bank active,
Gapless data,
tCK = Min.,
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
535
—
mA
460
Burst Write Current
(Average Power
Supply Current)
MB81P643287-50
MB81P643287-60
IDD4W
Burst Length = 4,
CAS Latency = 3,
All bank active,
Gapless data,
tCK = Min.,
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
595
—
mA
505
Auto-refresh Current ^{MB81P643287-50}
(Average Power
Supply Current)
MB81P643287-60
Auto-refresh;
IDD5
tCK = Min.,
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
320
—
mA
270
Self-refresh Current
(Average Power Supply Current)
Self-refresh;
IDD6 CKE = VIL,
0 V ≤ VIN ≤ VDD
—
5 mA
Notes: *1. All voltages referenced to VSS.
*2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*3. IDD depends on the output termination or load conditions, clock cycle rate, and number of address and
command change within certain period. The specified values are obtained with the output open.
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