MB81P643287 Datasheet, PDF (17/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
s STATE DIAGRAM
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Second command
(same bank)
First
command
MRS
ACTV READ READA WRIT WRITA
BST
*1
PRE
PALL
REF
SELF
MRS
lMRD
lMRD
lMRD
lMRD
lMRD
lMRD
lMRD
ACTV
lRCD
*4
lRCD
lRCD
*4
lRCD
1
lRAS
lRAS
READ
*4
*3
*3, 4
*4
*4
1
1
lRWD
lRWD
1
1
1
READA
WRIT
*5, 6
BL/2 BL/2
+ lRP + lRP
*7
*4, 7
lWRD
lWRD
1
*4
1
*4
BL/2
+ lRP
*4
BL/2
+ lRP
*6
BL/2
+ lRP
*5, 6
BL/2
+ lRP
*4,7
lDPL
*4,7
lDPL
WRITA
*6
lWAL
lWAL
*4
lWAL
*4
lWAL
*6
lWAL
*6
lWAL
BST
*3
*3
*4
*4
1
1
lBSNC lBSNC
1
1
1
PRE
*5, 6
lRP
lRP
*4
*6
*5, 6
1
1
1
lRP
lRP
PALL
*5
lRPA
lRPA
*5
1
1
1
lRPA
lRPA
REF
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
SELFX
lXSNR lXSNR
lXSNR lXSNR lXSNR lXSNR lXSNR
Notes: *1. BL/2 = tCK × BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.)
*2. Assume PALL command does not affect any operation on the other bank(s).
*3. Assume no I/O conflict.
*4. lRAS must be satisfied.
*5. Assume all outputs are in High-Z state.
*6. Assume all other banks are in idle state.
*7. lDPL and lWRD are specified from last data input and assumed preceding pair of write data are masked
by DM0 to DM3 input.
Illegal Command
17