MB81P643287 Datasheet, PDF (27/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
s MODE REGISTER TABLE
MODE REGISTER SET
ADDRESS BA2 BA1 BA0 A10 A9 A8 A7
A6 to A4
A3
A2 to A0
REGISTER 0^*1 0^*1 0^*1 0 0 DR TE
CL
BT
BL
A6 A5 A4
00X
010
011
100
101
110
111
CAS Latency
(CL)
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
A2
A1
A0
Burst Length
(BL)
000
Reserved
001
2
010
4
011
8
1XX
Reserved
A7
Test Mode Entry (TE)
0 Normal Operation
1
Test Mode (Used for Supplier Test
Mode)
A3
Burst Type (BT)
0 Sequential (Wrap round, Binary up)
1 Reserved
A8
DLL RESET (DR)
0 Normal Operation
1 RESET DLL
EXTENDED MODE REGISTER SET (Note *4)
ADDRESS
BA2 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
EXTENDED MODE
REGISTER
0^*2
0^*2
1^*2
RESERVED *³
DE
A0
DLL Enable (DE)
0 DLL Enable
1 DLL Disable
*1: A combination of BA2 = BA1 = BA0 = 0 (Low) selects standard Mode Register.
*2: A combination of BA1 = BA2 = 0 and BA0 = 1 (High) selects Extended Mode Register.
*3: These RESERVED field in EMRS must be set as 0.
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