MB81P643287 Datasheet, PDF (39/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
Fig. 6 - AC TIMING of CLK & CLK
CLK
CLK
tCK
tCL
tCH
VX
VSWING (AC)
Note: Reference level for AC timings of clock are the cross point of CLK and CLK as specified in VX.
Fig. 7 - AC TIMING of Command Input & Address
tCK
CLK
VX
CLK
Input
(Controls &
Addresses)
tIS
tIH
Input Valid
VREF
VIH (AC)
VIL (AC)
Note: The cross point of CLK and CLK (VX) is used for command and address input.
The reference level of single ended input is VREF.
Fig. 8 - AC TIMING of Write Mode (Data Strobe, Write Data and Data Mask Input)
CLK
tCK
tCK
CLK
Input
(Controls &
Addresses)
DQS Input ^VREF
(@BL = 4)
tIS
tIH
Write Command
VREF
tDQSS
VIH (AC)
VIL (AC)
tDSPRES
tDSPREH
tDSPRE
VIL
tDSH
tDSCS
tDQSS
tDSL
tDSCH
tDSH
tDSPST
tDS tDH
tDS tDH
tDS tDH
tDS tDH
Input
(Data & DM)
Input Valid
tDIPW
Input Valid
tDIPW
Input Valid
tDIPW
Input Valid
tDIPW
VREF
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