MB81P643287 Datasheet, PDF (48/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAM - 10: WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 8)
CLK
CLK
Command
DQS (Iutput)
WRIT
tDQSS
Don't Care
NOP
IDPL(Min.)
PRE
IRP (Min.)
NOP
ACTV
See Note 1.
Don't Care
DM
Don't Care
Don't Care
DQ0 to DQ31
(Input)
Don't Care
D1 D2    
See Note 2.
Don't Care
Note: 1. DQS Input are not required from when Precharge command is issued.
2. This pair of write data must be masked prior to Precharge command.
TIMING DIAGRAM - 11: READ TO WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK
CLK
Command
DQS
Hi-Z
READ
IRWD (Min.)
NOP
CL
WRIT
tDQSS
NOP
DM
Don't Care
Hi-Z
DQ0 to DQ31
Q1 Q2 Q3 Q4
D1 D2 D3 D4
I/O open for bus turn-around
Note: lRWD defines a minimum delay from Read to Write command input applied to the same bank.
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