MB81P643287 Datasheet, PDF (33/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
AC PARAMETERS (FREQUENCY DEPENDANT) Note *9
Parameter
Notes Symbol
Clock High Time
*4 tCH
Clock Low Time
*4 tCL
DQS Low to High Input Transition
Setup Time from CLK
*4, *10 tDQSS
DQS Low Input Pulse Width
tDSL
DQS High Input Pulse Width
tDSH
DQS First Low Input Hold Time
(Input Preamble Hold Time)
*4 tDSPREH
DQS First Low Input Pulse Width
(Input Preamble Pulse Width)
tDSPRE
DQS Last Low Input Hold Time
(Input Postamble Hold Time)
tDSPST
DQS Access Time from Clock
*4 tQSCK
DQS Output Valid Time
tQSV
DQS Output in Low-Z
(Output Preamble Setup Time)
*4, *11 tQSLZ
DQS First Low Output Hold Time
(Output Preamble Hold Time)
*4 tQSPRE
DQS Last Low Output Hold Time
(Output Postamble Hold Time)
*4, *12 tQSPST
DQS Last Low Output in High-Z
from CLK or CLK
*12 tQSHZ
DQ Access Time from CLK & CLK
*4 tACC
DQ Access Time from DQS
*5 tQSQ
DQ Output Data Valid Time from DQS
tDV
DQ Output in Low-Z
*4, *11 tLZ
DQ Output in High-Z
*4, *12 tHZ
DQ & DM Input Pulse Width
tDIPW
DQS Falling Edge to Clock Hold Time
tDSCH
DQS Falling Edge to Clock Setup Time
tDSCS
Min.
0.45 × tCK
0.45 × tCK
0.75 × tCK
0.4 × tCK
0.4 × tCK
0.25 × tCK
0.4 × tCK
0.4 × tCK
- 0.1 × tCK - 0.2
0.3 × tCK
- 0.1 × tCK - 0.2
0.9 × tCK - 0.2
0.4 × tCK - 0.2
—
- 0.1 × tCK - 0.2
- 0.1 × tCK
0.3 × tCK
- 0.1 × tCK - 0.2
- 0.1 × tCK - 0.2
0.4 × tCK
0.2 × tCK
(1.5 ns Min.)
0.2 × tCK
(1.5 ns Min.)
Max.
—
—
1.25 × tCK
—
—
—
Unit
ns
ns
ns
ns
ns
ns
—
ns
—
ns
0.1 × tCK + 0.2
ns
—
ns
—
ns
1.1 × tCK + 0.2
ns
0.6 × tCK + 0.2
ns
0.1 × tCK + 0.2
ns
0.1 × tCK + 0.2
ns
0.1 × tCK
ns
—
ns
—
ns
0.1 × tCK + 0.2
ns
—
ns
—
ns
—
ns
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