MB81P643287 Datasheet, PDF (58/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
VCC
CAS
TIMING DIAGRAM - 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence
and normal operation
Pause 100 µs
tTS
tTH
HL
Test Mode
tEPD
CS
L
PD
CLK
L
*3
tETD
CLK
or
CLK
CLK
*2
Entry
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, CKE pins will have some
problems.
*2. PRE or PALL commands must not be asserted. Test mode is disable by those commands.
*3. Outputs must be disabled by CS = H or CKE = L before Exit.
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