MB81P643287 Datasheet, PDF (59/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAM - 3: OUTPUT CONTROL (1)
VDD
CAS
CS
Entry
CAS must not brought from High to Low
DQ turn to Low-Z at CS = L and CKE = H
DQ turn to High-Z at CS = H
CKE
DQ0 to DQ31
DQS0 to DQS3
Memory device
output buffer status
This is not bus line level
High-Z
High-Z
tTLZ
Time (a)
Low-Z
Time (b)
tTHZ
High-Z
Time (c)
VDD
CAS
CS
CKE
TIMING DIAGRAM - 4: OUTPUT CONTROL (2)
Entry
CAS must not brought from High to Low
DQ turn to Low-Z at CS = L and CKE = H
DQ turn to High-Z at CKE = L
DQ0 to DQ31
DQS0 to DQS3
Memory device
output buffer status
High-Z
High-Z
tTLZ
Time (a)
Low-Z
Time (b)
tTHZ
High-Z
Time (c)
This is not bus line level
59