MB81P643287 Datasheet, PDF (54/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
COMMAND TRUTH TABLE Note *1
Control
CAS CS CKE WE
Input
RAS
A0 to A10,
BA0 to BA2
DM0
to
DM3
SCITT mode entry H→L *² L L
X
X
X
X
SCITT mode exit L→H *³ H ^*5 L ^*5 X
X
X
X
SCITT mode
output enable *⁴
L
LH V
V
V
V
CLK
H
L
X
V
CLK
L
H
X
V
Output
DQ0
to
DQ31
DQS0
to
DQS3
X
X
X
X
V
V
Notes: *1. L = Logic Low, H = Logic High, V = Valid, X = either L or H
*2. The SCITT mode entry command assumes the first CAS falling edge with CS = CKE = L and CLK,CLK
signals are complementary after power on.
*3. The SCITT mode exit command assumes the first CAS rising edge after the test mode entry.
*4. Refer the test code table.
*5. CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
54