MB81P643287 Datasheet, PDF (18/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTIPLE BANK OPERATION
Second command
(other bank)
*10
MRS
*8
*8
*8
ACTV READ READA WRIT
*8
WRITA
*9
BST
*2, 9
PRE PALL
First
command
REF
SELF
MRS
lMRD
lMRD
lMRD
lMRD
lMRD
lMRD
lMRD
ACTV
*6
*11
*11
*11
*11
*11
lRRD
1
1
1
1
1
1
lRAS
READ
*6
*3
*3
*4
1
1
1
lRWD
lRWD
1
1
1
READA
WRIT
*5, 6
BL/2 +
lRP
*6
1
*4
1
*4
1
* 3, 4
lRWD
* 3, 4
lRWD
*6
*7
*7
1
lWRD
lWRD
1
1
*6
*5, 6
1 BL/2 + BL/2 + BL/2 +
lRP
lRP
lRP
*4,7
1
lDPL
WRITA
BST
*6
lWAL
*6
*4
*4
1 BL/2 BL/2
+ lWRD + lWRD
*4
1
*4
1
*6
*11
*11
*3, 11
*3, 11
1
1
1
lBSNC lBSNC
1
*6
*6
1
lWAL
lWAL
lWAL
*4
1
1
PRE
*5, 6
*6
*11
*11
*3, 11
*3, 11
*11
lRP
1
1
1
1
1
1
1
*4
1
*6
lRP
*5, 6
lRP
PALL
*5
lRPA
lRPA
*5
1
1
1
lRPA
lRPA
REF
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
SELFX
lXSNR lXSNR
lXSNR lXSNR lXSNR lXSNR lXSNR
18