MB81P643287 Datasheet, PDF (42/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
s TIMING DIAGRAMS
TIMING DIAGRAM - 1: COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
CLK
Address
Row
Address
lRCD (Min.)
lCCD (Min.)
lCCD
lCCD
lCCD
Column Column Column Column Column
Address Address Address Address Address
RAS
CAS
Note: lCCD, CAS to CAS address delay, is applicable to the same bank access and
it can be one or more clock period.
CLK
CLK
Address
BA0, BA1
TIMING DIAGRAM - 2: DIFFERENT BANK ADDRESS INPUT DELAY
Row
Address
Bank 0
lRRD (Min.)
lRCD (Min.)
lCBD (Min.)
lCBD
lCBD
lCBD
Row
Column Column Column Column
Address Address Address Address Address
lRCD (Min.)
Bank 1 Bank 0 Bank 1 Bank 2 bank 3
RAS
CAS
42