MB81P643287 Datasheet, PDF (56/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
AC SPECIFICATION
Parameter
Description
tTS
Test mode entry set up time
tTH
Test mode entry hold time
tEPD
Test mode exit to power on sequence delay time
tTLZ
CS, CKE to output in Low-Z time
tTHZ
CS, CKE to output in High-Z time
tTCA
Test mode access time from control signals
(clock enable & chip select)
tTIA
Test mode Input access time
tTOH
Test mode Output Hold time
tETD
Test mode entry to test delay time
tTIH
Test mode input hold time
Min.
10
10
10
0
0
—
—
0
10
30
Max.
—
—
—
—
20
40
20
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
56