MB81P643287 Datasheet, PDF(51/65 Page) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

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MB81P643287 Datasheet, PDF (51/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

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MB81P643287-50/-60

CLK

Command

TIMING DIAGRAM - 16: AUTO-REFRESH ENTRY AND EXIT

IRFC (Min.)

REF

NOP

Any

CKE

CLK

TIMING DIAGRAM - 17: SELF-REFRESH ENTRY AND EXIT

IRFC (Min.)

tQCKEH

tIS

tPDEX

IXSNR or ISCD *

Command

NOP

SELF

Don't Care

NOP

ACTV

Hi-Z

DQS (Output)

DQ0 to DQ31

(Output)

Hi-Z

Last Data Output

Note * :CKE must maintain High level and stable clock must be provided during the lSCD period.

After Self-refresh exit, lXSNR must be satisfied for at least specified period before any command

(except for read) input.

TIMING DIAGRAM - 18: MODE REGISTER SET

CLK

Command

IMRD

NOP

MRS

NOP

Any

Note: MRS command must be issued after the last data is appeared on each DQ.

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