MB81P643287 Datasheet, PDF (37/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure and stable
clock input with constant clock period and with 50% duty cycle.
*2. Access Times assume input slew rate of 1ns/volt between VREF+0.35V to VREF-0.35V, where VREF is
VDDQ/2, with SSTL_2 output load conditions. Refer to AC TEST LOAD CIRCUIT.
*3. VREF = 1.25V is a typical reference level for measuring timing of input signals.
Transition times are measured between VIH(Min.) and VIL(Max.) unless otherwise noted.
Refer to AC TEST CONDITIONS.
*4. This parameter is measured from the cross point of CLK and CLK input.
*5. This parameter is measured from signal transition point of DQS0 to DQS3 input crossing VREF level.
*6. The specific requirement is that DQS be valid (HIGH or LOW) on or before this CLK edge. The case
shown (DQS going from High-Z to logic LOW) applies when no writes were previously in progress on
the bus. If a previous write was in progress, DQS could be HIGH at this time, depending on tDSS.
*7. tT is defined as the transition time between VIH (AC)(Min.) and VIL (AC)(Max.).
*8. Total of 4096 REF command must be issued within tREF (Max.). tAREF is a reference value for distributed
refresh and specifies the time between one REF command to next REF command except for a condition
where CKE = Low during Self-refresh mode.
*9. This parameter is scalable by actual clock period (tCK) and affected by an abrupt change of duty cycle,
jitters on clock input, TA and level of VDD and VDDQ.The internal DLL circuit can adjust delay time against
the change of following condition :
TA < 0.1 °C / 20 ns,
VDD < 1 mV / 10 ns,
VDDQ < 1 mV / 10 ns,
if change rate is bigger than these values, frequency dependent AC parameters affected by DLL jitters.
*10. More than 2 signal edge of DQS0 to DQS3 should not be input within 1 clock (tCK) cycle.
*11. Low-Z (Low Impedance State) is specified and measured at VTT ± 200mV.
*12. tQSPST, tQSHZ and tHZ are specified where output buffer is no longer driven.
*13. Actual clock count of lRC will be sum of clock count of lRAS and lRP.
*14. Assume tDQSS = 1 × tCK. If actual tDQSS is within specified minimum and maximum range, those parameters
can be assumed tDQSS = 1 × tCK.
*15. Applicable also if device operating conditions such as supply voltages, case temperature, and/or clock
frequency (tCK difference must be 0.2 ns or less) is changed during any operation.
*16. Clock period must satisfy specified tCK and it must be stable.
*17. Assume BST is effective to read operation (issued prior to the end of burst read).
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