MB81P643287 Datasheet, PDF (5/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
s BLOCK DIAGRAM
Fig. 1 - MB81P643287 BLOCK DIAGRAM
CLK
CLK
CKE
CS
RAS
CAS
WE
AP
CLOCK
BUFFER
To each block
Enable
COMMAND
DECODER
CONTROL
SIGNAL
LATCH
MODE
REGISTER
Bank-7
RAS
Bank-1
Bank-0
CAS
WE
DRAM
CORE
(2048 × 128 × 32)
A0 to A10
BA0, BA1,
BA2
DM0 to
DM3
DQ0 to
DQ31
DQS0 to
DQS3
ADDRESS
BUFFER/
REGISTER
ROW
11
ADDRESS
I/O DATA
BUFFER/
REGISTER
&
DQS
GENERATOR
COLUMN
ADDRESS
COUNTER
COLUMN
7 ^ADDRESS
I/O
32
DLL
Clock Buffer
VDDQ, VSSQ
VDD
VREF
VSS/VSSQ
5