MB81P643287 Datasheet, PDF (23/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access and MB81P643287 read and write operations are burst oriented.
The burst mode is implemented by keeping the same Row address and by automatic strobing Column address
in every single clock edge till programmed burst length(BL). Access time of burst mode is specified as tACC. The
internal column address counter operation is determined by a mode register which defines burst type(BT) and
burst count length(BL) of 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst mode
to the next stage while the remaining burst count is more than 2, the following combinations will be required.
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Burst Write
Burst Write
Burst Read
Burst Write
Burst Read
Burst Write
Burst Write
Burst Read
Precharge
Precharge
Read Command
1st Step Burst Stop Command (BST)
2nd Step Write Command after lBSNC
Write Command
1st Step Data Mask Input
2nd Step Read Command after lWRD from last data input
Precharge Command
1st Step Data Mask Input
2nd Step Precharge Command after lDPL from last data input
The burst type is sequential only. The sequential mode is an incremental decoding scheme within a boundary
address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end
of boundary address and then wraps round to the least significant address(= 0). If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.
Burst Length
Starting Column Address
A2 A1 A0
Sequential Mode
XX0
2
XX1
0–1
1–0
X00
0–1–2–3
X01
4
X10
1–2–3–0
2–3–0–1
X11
3–0–1–2
000
001
0–1–2–3–4–5–6–7
1–2–3–4–5–6–7–0
010
2–3–4–5–6–7–0–1
011
8
100
3–4–5–6–7–0–1–2
4–5–6–7–0–1–2–3
101
5–6–7–0–1–2–3–4
110
111
6–7–0–1–2–3–4–5
7–0–1–2–3–4–5–6
23