MB81P643287 Datasheet, PDF (43/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAM - 3: READ (EXAMPLE @ BL = 4)
CLK
CLK
CKE _High
Command
ICCD (Min.)
READ
READ
NOP
DQS
Hi-Z
(Output)
@CL = 2
DQ0 to DQ31 _Hi-Z
(Output)
@CL = 2
DQS
Hi-Z
(Output)
@CL = 3
DQ0 to DQ31 _Hi-Z
(Output)
@CL = 3
CAS Latency
CAS Latency
Preamble
Q1 Q2 Q1 Q2 Q3 Q4
CAS Latency
CAS Latency
Preamble
Q1 Q2 Q1 Q2 Q3 Q4
Note: CAS Latency is defined from Read command to first rising edge of DQS0 to DQS3 output.
Preamble is 1 × tCK length and starts driving Low level.
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