MB81P643287 Datasheet, PDF (22/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
BANK ADDRESS (BA0 to BA2)
The MB81P643287 has eight internal banks and each bank is organized as 256K words by 32-bit.
Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT
or WRITA), and Precharge(PRE) command.
ADDRESS INPUTS (A0 to A10)
Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix within each
bank. A total of twenty address input signals are required to decode such a matrix. DDR SDRAM adopts an
address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV),
eleven Row addresses are initially latched as well as three Bank addresses and the remainder of seven Column
addresses are then latched by a Column address strobe command of either a read command (READ or READA)
or write command (WRIT or WRITA).
DATA STROBE (DQS0 to DQS3)
DQS0 to DQS3 are bi-directional signal and represent byte 0 to byte 3, respectively. During Read operation, DQS0
to DQS3 provides the read data strobe signal that is intended to use input data strobe signal at the receiver
circuit of the controller(s). It turns Low before first data is coming out and toggle High to Low or Low to High till
end of burst read. Refer to Figure 3 for the timing example.
The CAS Latency is specified to the first Low to High transition of these DQS0 to DQS3 output.
During the write operation, DQS0 to DQS3 are used to latch write data and Data Mask signals. As well as the
behavior of read data strobe, the first rising edge of DQS0 to DQS3 input latches first input data and following
falling edge of DQS0 to DQS3 signal latches second input data. This sequence shall be continued till end of burst
count. Therefore, DQS0 to DQS3 must be provided from controller that drives write data.
Note that DQS0 to DQS3 input signal should not be tristated from High at the end of write mode.
DATA INPUTS AND OUTPUTS (DQ0 to DQ31)
Input data is latched by DQS0 to DQS3 input signal and written into memory at the clock following the write
command input. Output data is obtained together with DQS0 to DQS3 output signals at programmed read CAS
latency.
The polarity of the output data is identical to that of the input. Data is valid after DQS0 to DQS3 output signal
transitions (tQSQ) as specified in Data Valid Time (tDV).
WRITE DATA MASK (DM0 to DM3)
DM0 to DM3 are active High enable inputs and represent byte 0 to byte 3 respectively. DM0 to DM3 have a data
input mask function, and are also sampled by DQS0 to DQS3 input signal together with input data.
During write cycle, DM0 to DM3 provide byte mask function. When DMx = High is latched by a DQS0 to DQS3
signal edge, data input at the same edge of DQS0 to DQS3 is masked.
During read cycle, all DM0 to DM3 are inactive and do not have any effect on read operation.
Refer to DM0 to DM3 TRUTH TABLE.
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