MB81P643287 Datasheet, PDF (35/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
LATENCY
(The latency values on these parameters are fixed regardless of clock period.)
Parameter
Notes Symbol
MB81P643287-50
Min.
Max.
MB81P643287-60
Unit
Min.
Max.
CL = 3
6
—
6
—
tCK
RAS Cycle Time
*13
lRC
CL = 2
5
—
5
—
tCK
RAS Active Time
CL = 3
4
11000
4
11000 tCK
lRAS
CL = 2
3
7333
3
7333
tCK
RAS Precharge Time
lRP
2
—
2
—
tCK
CL = 3
3
—
3
—
tCK
RAS to CAS Delay Time
lRCD
CL = 2
2
—
2
—
tCK
RAS to RAS Bank Active Delay Time
lRRD
1
—
1
—
tCK
CL = 3
4
—
4
—
tCK
Precharge All Bank to Active
lRPA
CL = 2
3
—
3
—
tCK
Read Command to Write
Command Delay
CL = 3
BL/2+3
—
BL/2+3
—
tCK
lRWD
CL = 2
BL/2+2
—
BL/2+2
—
tCK
Last Input Data to Read Command
Delay
*14 _lWRD
2.5
—
2.5
—
tCK
Last Input Data to Precharge Command
Lead Time
*14
lDPL
2.5
—
2.5
—
tCK
Write with Auto Precharge Command to
Active command Delay
*14
lWAL
BL/2+3+lRP
—
BL/2+3+lRP
—
tCK
Mode Register Access to Next Command
Input Delay
lMRD
2
—
2
—
tCK
CAS to CAS Delay
lCCD
1
—
1
—
tCK
CAS Bank Delay
lCBD
1
—
1
—
tCK
Precharge Power Down Exit to Next
Command Input Delay
lPDEXP
2
—
2
—
tCK
Minimum Stable Clock Input After Self- *15
refresh Exit Before READ Command Input
lSCD
400
—
400
—
tCK
Minimum Stable Clock Input After Self-
refresh Exit Before non-READ Command
lXSNR
12
—
12
—
tCK
Input
Minimum Stable Clock Input for tCK ≤ 7.5ns
400
—
400
—
tCK
DLL Lock-on in Power-up
lPCD
Initialization sequence. *16 ^{tCK ≤ 10.5ns}
630
—
630
—
tCK
Auto-refresh Cycle Time
lRFC
12
—
12
—
tCK
35