MC9S08DZ128 Datasheet, PDF (77/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Memory
Table 4-13. FCDIV Register Field Descriptions
Field
7
DIVLD
6
PRDIV8
5:0
DIV
Description
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH and EEPROM.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH and EEPROM.
Prescale (Divide) FLASH and EEPROM Clock by 8 (This bit is write once.)
0 Clock input to the FLASH and EEPROM clock divider is the bus rate clock.
1 Clock input to the FLASH and EEPROM clock divider is the bus rate clock divided by 8.
Divisor for FLASH and EEPROM Clock Divider — The FLASH and EEPROM clock divider divides the bus rate
clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting
frequency of the internal FLASH and EEPROM clock must fall within the range of 200 kHz to 150 kHz for proper
FLASH and EEPROM operations. Program/Erase timing pulses are one cycle of this internal FLASH and
EEPROM clock which corresponds to a range of 5 μs to 6.7 μs. The automated programming logic uses an
integer number of these pulses to complete an erase or program operation. See Equation 4-1 and Equation 4-2.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
77