MC9S08DZ128 Datasheet, PDF (180/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
factor, as selected by the DRS and DMX32 bits, times the internal reference frequency. The MCGLCLK
is derived from the FLL and the PLL is disabled in a low power state.
8.4.1.4 FLL Bypassed External (FBE)
In FLL bypassed external (FBE) mode, the MCGOUT clock is derived from the external reference clock
and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire
its target frequency while the MCGOUT clock is driven from the external reference clock.
The FLL bypassed external mode is entered when all the following conditions occur:
• CLKS bits are written to 10
• IREFS bit is written to 0
• PLLS bit is written to 0
• RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
• LP bit is written to 0
In FLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The
external reference clock which is enabled can be an external crystal/resonator or it can be another external
clock source.The FLL clock is controlled by the external reference clock, and the FLL clock frequency
locks to a multiplication factor, as selected by the DRS and DMX32 bits, times the external reference
frequency, as selected by the RDIV, RANGE and DIV32 bits. The MCGLCLK is derived from the FLL
and the PLL is disabled in a low power state.
8.4.1.5 PLL Engaged External (PEE)
The PLL engaged external (PEE) mode is entered when all the following conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 0
• PLLS bit is written to 1
• RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz
In PLL engaged external mode, the MCGOUT clock is derived from the PLL clock which is controlled by
the external reference clock. The external reference clock which is enabled can be an external
crystal/resonator or it can be another external clock source The PLL clock frequency locks to a
multiplication factor, as selected by the VDIV bits, times the external reference frequency, as selected by
the RDIV, RANGE and DIV32 bits. If BDM is enabled then the MCGLCLK is derived from the DCO
(open-loop mode) divided by two. If BDM is not enabled then the FLL is disabled in a low power state.
In this mode, the DRST bit reads 0 regardless of whether the DRS bit is set to 1 or 0.
MC9S08DZ128 Series Data Sheet, Rev. 1
180
Freescale Semiconductor