MC9S08DZ128 Datasheet, PDF (186/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
— If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and
EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the
external clock source has finished its initialization cycles and stabilized. Typical crystal startup
times are given in Appendix A, “Electrical Characteristics”.
— If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before
moving on.
— If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the
CLKST bits have changed to %10 indicating the external reference clock has been
appropriately selected. Although the FLL is bypassed in FBE mode, it is still on and will lock
in FBE mode.
5. Write to the MCGT register to determine the DCO output (MCGOUT) frequency range.
— By default, with DMX32 (bit 5) cleared to 0, the FLL multiplier for the DCO output is 1024.
For greater flexibility, if a mid-range FLL multiplier of 512 is desired instead, clear the DRS
bit (bit 0) to 0 for a DCO output frequency of 16.78 MHz.
— When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that
can be achieved with a 32.768 kHz reference is desired, clear the DRS bit (bit 0) to 0 and set
the DMX32 bit (bit 5) to 1. The resulting DCO output (MCGOUT) frequency with the new
multiplier of 608 will be 19.92 MHz.
— When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that
can be achieved with a 32.768 kHz reference is desired, set the DRS bit (bit 0) to 1 and set the
DMX32 bit (bit 5) to 1. The resulting DCO output (MCGOUT) frequency with the new
multiplier of 1216 will be 39.85 MHz.
6. Wait for the LOCK bit in MCGSC to become set, indicating that the FLL has locked to the new
multiplier value designated by the DRS and DMX32 bits.
NOTE
Setting DIV32 (bit 4) in MCGC3 is strongly recommended for FLL external
modes when using a high frequency range (RANGE = 1) external reference
clock. The DIV32 bit is ignored in all other modes.
To change from FEI clock mode to FBI clock mode, follow this procedure:
1. Change the CLKS bits in MCGC1 to %01 so that the internal reference clock is selected as the
system clock source.
2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal
reference clock has been appropriately selected.
8.5.2 Using a 32.768 kHz Reference
In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor
of 1024, the DCO output (MCGOUT) frequency is 33.55 MHz at high-range. If DRS is cleared to 0, the
multiplication factor is halved to 512, and the resulting DCO output frequency is 16.78 Mhz at mid-range.
Setting the DMX32 bit in MCGT to 1 increases the FLL multiplication factor to allow the 32.768 kHz
reference to achieve its maximum DCO output frequency. When the DRS bit is set, the 32.768 kHz
MC9S08DZ128 Series Data Sheet, Rev. 1
186
Freescale Semiconductor