MC9S08DZ128 Datasheet, PDF (147/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Central Processor Unit (S08CPUV5)
7.3 Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, memory, status and
control registers, and input/output (I/O) ports share a single 64-Kbyte CPU address space. This
arrangement means that the same instructions that access variables in RAM can also be used to access I/O
and control registers or nonvolatile program space.
NOTE
For more information about extended addressing modes, see the Memory
Management Unit section in the Memory chapter.
MCU derivatives with more than 64-Kbytes of memory also include a memory management unit (MMU)
to support extended memory space. A PPAGE register is used to manage 16-Kbyte pages of memory which
can be accessed by the CPU through a 16-Kbyte window from 0x8000 through 0xBFFF. The CPU includes
two special instructions (CALL and RTC). CALL operates like the JSR instruction except that CALL saves
the current PPAGE value on the stack and provides a new PPAGE value for the destination. RTC works
like the RTS instruction except RTC restores the old PPAGE value in addition to the PC during the return
from the called routine. The MMU also includes a linear address pointer register and data access registers
so that the extended memory space operates as if it was a single linear block of memory. For additional
information about the MMU, refer to the Memory chapter of this data sheet.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
of an operand for a test and then use relative addressing mode to specify the branch destination address
when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
7.3.1 Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU
registers so the CPU does not need to access memory to get any operands.
7.3.2 Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit
offset value is located in the memory location immediately following the opcode. During execution, if the
branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current
contents of the program counter, which causes program execution to continue at the branch destination
address.
7.3.3 Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object
code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
147