MC9S08DZ128 Datasheet, PDF (15/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Section Number
Title
Page
12.3 Register Definition .........................................................................................................................257
12.3.1 MSCAN Control Register 0 (CANCTL0) ......................................................................257
12.3.2 MSCAN Control Register 1 (CANCTL1) ......................................................................260
12.3.3 MSCAN Bus Timing Register 0 (CANBTR0) ...............................................................261
12.3.4 MSCAN Bus Timing Register 1 (CANBTR1) ...............................................................262
12.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER) .............................................265
12.3.6 MSCAN Transmitter Flag Register (CANTFLG) ..........................................................266
12.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER) ........................................267
12.3.8 MSCAN Transmitter Message Abort Request Register (CANTARQ) ...........................268
12.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) .................269
12.3.10MSCAN Transmit Buffer Selection Register (CANTBSEL) .........................................269
12.3.11MSCAN Identifier Acceptance Control Register (CANIDAC) ......................................270
12.3.12MSCAN Miscellaneous Register (CANMISC) ..............................................................271
12.3.13MSCAN Receive Error Counter (CANRXERR) ............................................................272
12.3.14MSCAN Transmit Error Counter (CANTXERR) ..........................................................273
12.3.15MSCAN Identifier Acceptance Registers (CANIDAR0-7) ............................................273
12.3.16MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) .................................274
12.4 Programmer’s Model of Message Storage .....................................................................................275
12.4.1 Identifier Registers (IDR0–IDR3) ...................................................................................278
12.4.2 IDR0–IDR3 for Standard Identifier Mapping .................................................................280
12.4.3 Data Segment Registers (DSR0-7) .................................................................................281
12.4.4 Data Length Register (DLR) ...........................................................................................282
12.4.5 Transmit Buffer Priority Register (TBPR) ......................................................................283
12.4.6 Time Stamp Register (TSRH–TSRL) .............................................................................283
12.5 Functional Description ...................................................................................................................284
12.5.1 General ............................................................................................................................284
12.5.2 Message Storage .............................................................................................................285
12.5.3 Identifier Acceptance Filter .............................................................................................288
12.5.4 Modes of Operation ........................................................................................................295
12.5.5 Low-Power Options ........................................................................................................296
12.5.6 Reset Initialization ..........................................................................................................302
12.5.7 Interrupts .........................................................................................................................302
12.6 Initialization/Application Information ...........................................................................................304
12.6.1 MSCAN initialization .....................................................................................................304
12.6.2 Bus-Off Recovery ...........................................................................................................305
Chapter 13
Serial Peripheral Interface (S08SPIV3)
13.1 Introduction ....................................................................................................................................307
13.1.1 Features ...........................................................................................................................309
13.1.2 Block Diagrams ..............................................................................................................309
13.1.3 SPI Baud Rate Generation ..............................................................................................311
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
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