MC9S08DZ128 Datasheet, PDF (399/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Debug Module (S08DBGV3) (128K)
1 _{In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.}
Table 18-6. DBGCBL Field Descriptions
Field
Bits 7–0
Description
Comparator B Low Compare Bits — The Comparator B Low compare bits control whether Comparator B will
compare the address bus or data bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0, compares to data if in Full mode
1 Compare corresponding address bit to a logic 1, compares to data if in Full mode
18.3.3.5 Debug Comparator C High Register (DBGCCH)
Module Base + 0x0004
7
R
Bit 15
W
6
Bit 14
5
Bit 13
4
Bit 12
3
Bit 11
2
Bit 10
1
Bit 9
0
Bit 8
POR
or non-
0
0
0
0
0
0
0
0
end-run
Reset
end-run¹
U
U
U
U
U
U
U
U
Figure 18-6. Debug Comparator C High Register (DBGCCH)
1 _{In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.}
Table 18-7. DBGCCH Field Descriptions
Field
Description
Bits 15–8
Comparator C High Compare Bits — The Comparator C High compare bits control whether Comparator C will
compare the address bus bits [15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
399