MC9S08DZ128 Datasheet, PDF (134/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output Control
6.5.9.5 Port J Drive Strength Selection Register (PTJDS)
R
W
Reset:
7
PTJDS7
0
6
PTJDS6
5
PTJDS5
4
PTJDS4
3
PTJDS3
2
PTJDS2
1
PTJDS1
0
0
0
0
0
0
Figure 6-56. Drive Strength Selection for Port J Register (PTJDS)
Table 6-54. PTJDS Register Field Descriptions
0
PTJDS0
0
Field
Description
7:0
PTJDS[7:0]
Output Drive Strength Selection for Port J Bits — Each of these control bits selects between low and high
output drive for the associated PTJ pin. For port J pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port J bit n.
1 High output drive strength selected for port J bit n.
6.5.9.6 Port J Interrupt Status and Control Register (PTJSC)
7
6
5
4
3
2
1
0
R
0
0
0
0
PTJIF
0
PTJIE
PTJMOD
W
PTJACK
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-57. Port J Interrupt Status and Control Register (PTJSC)
Table 6-55. PTJSC Register Field Descriptions
Field
Description
3
PTJIF
2
PTJACK
1
PTJIE
0
PTJMOD
Port J Interrupt Flag — PTJIF indicates when a port J interrupt is detected. Writes have no effect on PTJIF.
0 No port J interrupt detected.
1 Port J interrupt detected.
Port J Interrupt Acknowledge — Writing a 1 to PTJACK is part of the flag clearing mechanism. PTJACK always
reads as 0.
Port J Interrupt Enable — PTJIE determines whether a port J interrupt is requested.
0 Port J interrupt request not enabled.
1 Port J interrupt request enabled.
Port J Detection Mode — PTJMOD (along with the PTJES bits) controls the detection mode of the port J
interrupt pins.
0 Port J pins detect edges only.
1 Port J pins detect both edges and levels.
MC9S08DZ128 Series Data Sheet, Rev. 1
134
Freescale Semiconductor