MC9S08DZ128 Datasheet, PDF (416/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Debug Module (S08DBGV3) (128K)
in the DBGCNT register at the end of a trace run, the number of valid words can be determined. The FIFO
data is read by optionally reading the DBGFX and DBGFH registers followed by the DBGFL register.
Each time the DBGFL register is read the FIFO is shifted to allow reading of the next word however the
count does not decrement. In event-only trigger modes where the FIFO will contain only the data bus
values stored, to read the FIFO only DBGFL needs to be accessed.
The FIFO is normally only read while ARM and ARMF=0, however reading the FIFO while the DBG
module is armed will return the data value in the oldest location of the FIFO and the TBC will not allow
the FIFO to shift. This action could cause a valid entry to be lost because the unexpected read blocked the
FIFO advance.
If the DBG module is not armed and the DBGFL register is read, the TBC will store the current opcode
address. Through periodic reads of the DBGFX, DBGFH, and DBGFL registers while the DBG module
is not armed, host software can provide a histogram of program execution. This is called profile mode.
Since the full 17-bit address and the signal that indicates whether an address is in paged extended memory
are captured on each FIFO store, profile mode works correctly over the entire extended memory map.
18.4.6 Interrupt Priority
When TRGSEL is set and the DBG module is armed to trigger on begin- or end-trigger types, a trigger is
not detected in the condition where a pending interrupt occurs at the same time that a target address reaches
the top of the instruction pipe. In these conditions, the pending interrupt has higher priority and code
execution switches to the interrupt service routine.
When TRGSEL is clear and the DBG module is armed to trigger on end-trigger types, the trigger event is
detected on a program fetch of the target address, even when an interrupt becomes pending on the same
cycle. In these conditions, the pending interrupt has higher priority, the exception is processed by the core
and the interrupt vector is fetched. Code execution is halted before the first instruction of the interrupt
service routine is executed. In this scenario, the DBG module will have cleared ARM without having
recorded the change-of-flow that occurred as part of the interrupt exception. Note that the stack will hold
the return addresses and can be used to reconstruct execution flow in this scenario.
When TRGSEL is clear and the DBG module is armed to trigger on begin-trigger types, the trigger event
is detected on a program fetch of the target address, even when an interrupt becomes pending on the same
cycle. In this scenario, the FIFO captures the change of flow event. Because the system is configured for
begin-trigger, the DBG remains armed and does not break until the FIFO has been filled by subsequent
change of flow events.
18.5 Resets
The DBG module cannot cause an MCU reset.
There are two different ways this module will respond to reset depending upon the conditions before the
reset event. If the DBG module was setup for an end trace run with DBGEN=1 and BEGIN=0, ARM,
ARMF, and BRKEN are cleared but the reset function on most DBG control and status bits is overridden
so a host development system can read out the results of the trace run after the MCU has been reset. In all
other cases including POR, the DBG module controls are initialized to start a begin trace run starting from
when the reset vector is fetched. The conditions for the default begin trace run are:
MC9S08DZ128 Series Data Sheet, Rev. 1
416
Freescale Semiconductor