MC9S08DZ128 Datasheet, PDF (397/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Debug Module (S08DBGV3) (128K)
18.3.3 Register Descriptions
This section consists of the DBG register descriptions in address order.
Note: For all registers below, consider: U = Unchanged, bit maintain its value after reset.
18.3.3.1 Debug Comparator A High Register (DBGCAH)
Module Base + 0x0000
7
R
Bit 15
W
6
Bit 14
5
Bit 13
4
Bit 12
3
Bit 11
2
Bit 10
1
Bit 9
0
Bit 8
POR
or non-
1
1
1
1
1
1
1
1
end-run
Reset
end-run¹
U
U
U
U
U
U
U
U
Figure 18-2. Debug Comparator A High Register (DBGCAH)
1 _{In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.}
Table 18-3. DBGCAH Field Descriptions
Field
Description
Bits 15–8
Comparator A High Compare Bits — The Comparator A High compare bits control whether Comparator A will
compare the address bus bits [15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
18.3.3.2 Debug Comparator A Low Register (DBGCAL)
Module Base + 0x0001
7
R
Bit 7
W
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
0
Bit 0
POR
or non-
1
1
1
1
1
1
1
0
end-run
Reset
end-run¹
U
U
U
U
U
U
U
U
Figure 18-3. Debug Comparator A Low Register (DBGCAL)
1 _{In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.}
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
397