MC9S08DZ128 Datasheet, PDF (437/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued)
Num C
Rating
Symbol
Min
Typical
Max
Unit
15 D PLL reference frequency range
f_{pll_ref}
1.0
—
2.0
MHz
16
RMS frequency variation of a single clock cycle measured
T _{2 ms after reference edge.6}
f_{pll_cycjit_2ms}
—
0.590⁵
—
%f_pll
17
T
Maximum frequency variation averaged over 2 ms
window.
f_{pll_maxjit_2ms}
—
0.001
—
%f_pll
18
T
RMS frequency variation of a single clock cycle measured
625 ns after reference edge.⁷
f_{pll_cycjit_625ns}
—
0.566⁵
—
%f_pll
19
T
Maximum frequency variation averaged over 625 ns
window.
f_{pll_maxjit_625ns}
—
0.113
—
%f_pll
20 D _{Lock entry frequency tolerance} ⁸
D_lock
± 1.49
—
± 2.98
%
21 D _{Lock exit frequency tolerance} ⁹
D_unl
± 4.47
—
± 5.97
%
22 D Lock time - FLL
t_{fll_lock}
—
—
t_{fll_acquire+}
1075(1/^fint_t)
s
1 _{This applies when TRIM register at value (0x80) and FTRIM control bit at value (0x0). These values load when in BDM modes.}
2 _{The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.}
3 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit}
is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a
crystal/resonator is being used as the reference, this specification assumes it is already running.
4 _{This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,}
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
5 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for a given interval.
These jitter measurements are based upon a 40 MHz MCGOUT clock frequency.
6 _{In some specifications, this value is described as, “Long term accuracy of PLL output clock (averaged over 2 ms)” with symbol}
“f_{pll_jitter_2ms}.” The parameter is unchanged, but the description has been changed for clarification purposes.
7 _{In some specifications, this value is described as “Jitter of PLL output clock measured over 625 ns” with symbol “fpll_jitter_625ns.”}
The parameter is unchanged, but the description has been changed for clarification purposes.
8 _{Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is}
already in lock, then the MCG may stay in lock.
9 _{Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.}
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
437