MC9S08DZ128 Datasheet, PDF (401/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Debug Module (S08DBGV3) (128K)
Table 18-9. DBGFH Field Descriptions
Field
Description
Bits 15–8 FIFO High Data Bits — The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register
is not used in event only modes and will read a $00 for valid FIFO words.
18.3.3.8 Debug FIFO Low Register (DBGFL)
Module Base + 0x0007
7
R Bit 7
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
0
Bit 0
W
POR
or non-
0
0
0
0
0
0
0
0
end-run
Reset
end-run¹
U
U
U
U
U
U
U
U
= Unimplemented or Reserved
Figure 18-9. Debug FIFO Low Register (DBGFL)
1 _{In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.}
Table 18-10. DBGFL Field Descriptions
Field
Bits 7–0
Description
FIFO Low Data Bits — The FIFO Low data bits contain the least significant byte of data in the FIFO. When
reading FIFO words, read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the
FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX
and DBGFH so it is not necessary to read them before reading DBGFL.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
401