MC9S08DZ128 Datasheet, PDF (173/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

8.3.3 MCG Trim Register (MCGTRM)
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
7
6
5
4
3
2
1
0
R
TRIM¹
W
Figure 8-5. MCG Trim Register (MCGTRM)
1 _{A value for TRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM}
mode, a default value of 0x80 is loaded.
Field
7:0
TRIM
Table 8-5. MCG Trim Register Field Descriptions
Description
MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock
period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary
value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in MCGSC as the FTRIM bit.
If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value
from the nonvolatile memory location to this register.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
173