MC9S08DZ128 Datasheet, PDF (394/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Debug Module (S08DBGV3) (128K)
• Ability to End-trace until reset and Begin-trace from reset
18.1.2 Modes of Operation
The on-chip ICE system can be enabled in all MCU functional modes. The DBG module is disabled if the
MCU is secure. The DBG module comparators are disabled when executing a Background Debug Mode
(BDM) command.
18.1.3 Block Diagram
Figure 18-1 shows the structure of the DBG module.
core_cpu_aob_14_t2
core_cpu_aob_15_t2
1
1
core_ppage_t2[2:0] ¹
DBG Read Data Bus
FIFO Data
Address Bus[16:0]¹
Write Data Bus
Read Data Bus
Read/Write
DBG Module Enable
mmu_ppage_sel¹
c ^{Address/Data/Control Registers control}
o
n
t
r
Comparator A
o
l
Comparator B
match_A
match_B
Comparator C
match_C
core_cof[1:0]
MCU in BDM
MCU reset
Change of Flow Indicators
event only
store
Trigger
Break
Control
Logic
Tag
Force
Instr. Lastcycle
Bus Clk
register
subtract 2
m
u
x
m
u
x
Write Data Bus
m
Read Data Bus
u
x
ppage_sel¹
8 deep
FIFO
m
u
x
addr[16:0]¹
Read DBGFL
Read DBGFH
Read DBGFX
FIFO Data
Read/Write
1. In 64K versions of this module there are only 16 address lines [15:0], there are no core_cpu_aob_14_t2,
core_cpu_aob_15_t2, core_ppage_t2[2:0], and ppage_sel signals.
Figure 18-1. DBG Block Diagram
18.2 Signal Description
The DBG module contains no external signals.
MC9S08DZ128 Series Data Sheet, Rev. 1
394
Freescale Semiconductor