MC9S08DZ128 Datasheet, PDF (415/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Debug Module (S08DBGV3) (128K)
1 _{When BRKEN = 0, TAG is do not care (x in the table).}
2 _{In end trace configurations (BEGIN = 0) where a CPU breakpoint is enabled (BRKEN = 1), TRGSEL should agree with TAG. In this case, where}
TRGSEL = 0 to select no opcode tracking qualification and TAG = 1 to specify a tag-type CPU breakpoint, the CPU breakpoint would not take
effect until sometime after the FIFO stopped storing values. Depending on program loops or interrupts, the delay could be very long.
3 _{In end trace configurations (BEGIN = 0) where a CPU breakpoint is enabled (BRKEN = 1), TRGSEL should agree with TAG. In this case, where}
TRGSEL = 1 to select opcode tracking qualification and TAG = 0 to specify a force-type CPU breakpoint, the CPU breakpoint would erroneously
take effect before the FIFO stopped storing values and the debug run would not complete normally.
4 In begin trace configurations (BEGIN = 1) where a CPU breakpoint is enabled (BRKEN = 1), TAG should not be set to 1. In begin trace debug
runs, the CPU breakpoint corresponds to the FIFO full condition which does not correspond to a taggable instruction fetch.
18.4.5 FIFO
The FIFO is an eight word deep FIFO. In all trigger modes except for event only, the data stored in the
FIFO will be change of flow addresses. In the event only trigger modes only the data bus value
corresponding to the event is stored. In event only trigger modes, the high byte of the valid data from the
FIFO will always read a 0x00 and the extended information byte in DBGFX will always read 0x00.
18.4.5.1 Storing Data in FIFO
In all trigger modes except for the event only modes, the address stored in the FIFO will be determined by
the change of flow indicators from the core. The signal core_cof[1] indicates the current core address is
the destination address of an indirect JSR or JMP instruction, or a RTS, RTC, or RTI instruction or interrupt
vector and the destination address should be stored. The signal core_cof[0] indicates that a conditional
branch was taken and that the source address of the conditional branch should be stored.
18.4.5.2 Storing with Begin-Trigger
Storing with Begin-Trigger can be used in all trigger modes. Once the DBG module is enabled and armed
in the begin-trigger mode, data is not stored in the FIFO until the trigger condition is met. Once the trigger
condition is met the DBG module will remain armed until 8 words are stored in the FIFO. If the
core_cof[1] signal becomes asserted, the current address is stored in the FIFO. If the core_cof[0] signal
becomes asserted, the address registered during the previous last cycle is decremented by two and stored
in the FIFO.
18.4.5.3 Storing with End-Trigger
Storing with End-Trigger cannot be used in event-only trigger modes. Once the DBG module is enabled
and armed in the end-trigger mode, data is stored in the FIFO until the trigger condition is met. If the
core_cof[1] signal becomes asserted, the current address is stored in the FIFO. If the core_cof[0] signal
becomes asserted, the address registered during the previous last cycle is decremented by two and stored
in the FIFO. When the trigger condition is met, the ARM and ARMF will be cleared and no more data will
be stored. In non-event only end-trigger modes, if the trigger is at a change of flow address the trigger event
will be stored in the FIFO.
18.4.5.4 Reading Data from FIFO
The data stored in the FIFO can be read using BDM commands provided the DBG module is enabled and
not armed (DBGEN=1 and ARM=0). The FIFO data is read out first-in-first-out. By reading the CNT bits
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
415