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MC9S08DZ128 Datasheet, PDF (189/458 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
a) BLPE: If a transition through BLPE mode is desired, ï¬rst set LP (bit 3) in MCGC2 to 1.
b) BLPE/PBE: MCGC3 = 0x58 (%01011000)
â PLLS (bit 6) set to 1, selects the PLL. At this time, with an RDIV value of %011, the FLL
reference divider of 256 is switched to the PLL reference divider of 8 (see Table 8-3),
resulting in a reference frequency of 8 MHz/ 8 = 1 MHz. In BLPE mode,changing the PLLS
bit only prepares the MCG for PLL usage in PBE mode
â DIV32 (bit 4) still set at 1. Because the MCG is in a PLL mode, the DIV32 bit is ignored.
Keeping it set at 1 makes transitions back into an FLL external mode easier.
â VDIV (bits 3-0) set to %1000, or multiply-by-32 because 1 MHz reference * 32= 32MHz.
In BLPE mode, the conï¬guration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
c) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to
PBE mode
d) PBE: Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the
PLLS clock is the PLL
e) PBE: Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
3. Lastly, PBE mode transitions into PEE mode:
a) MCGC1 = 0x18 (%00011000)
â CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
system clock source
b) Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected
to feed MCGOUT in the current clock mode
â Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-32,
MCGOUT = [(8 MHz / 8) * 32] / 1 = 32 MHz, and the bus frequency is MCGOUT / 2, or
16 MHz
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
189
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