|
MC9S08DZ128 Datasheet, PDF (140/458 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
|
◁ |
Chapter 6 Parallel Input/Output Control
6.5.11.3 Port L Pull Enable Register (PTLPE)
R
W
Reset:
7
PTLPE7
0
6
PTLPE6
5
PTLPE5
4
PTLPE4
3
PTLPE3
2
PTLPE2
1
PTLPE1
0
0
0
0
0
0
Figure 6-67. Internal Pull Enable for Port L Register (PTLPE)
Table 6-65. PTLPE Register Field Descriptions
0
PTLPE0
0
Field
Description
7:0
PTLPE[7:0]
Internal Pull Enable for Port L Bits â Each of these control bits determines if the internal pull-up device is
enabled for the associated PTL pin. For port L pins that are conï¬gured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port L bit n.
1 Internal pull-up device enabled for port L bit n.
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are conï¬gured.
6.5.11.4 Port L Slew Rate Enable Register (PTLSE)
R
W
Reset:
7
PTLSE7
0
6
PTLSE6
5
PTLSE5
4
PTLSE4
3
PTLSE3
2
PTLSE2
1
PTLSE1
0
0
0
0
0
0
Figure 6-68. Slew Rate Enable for Port L Register (PTLSE)
Table 6-66. PTLSE Register Field Descriptions
0
PTLSE0
0
Field
Description
7:0
PTLSE[7:0]
Output Slew Rate Enable for Port L Bits â Each of these control bits determines if the output slew rate control
is enabled for the associated PTL pin. For port L pins that are conï¬gured as inputs, these bits have no effect.
0 Output slew rate control disabled for port L bit n.
1 Output slew rate control enabled for port L bit n.
Note: Slew rate reset default values may differ between engineering samples and ï¬nal production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
MC9S08DZ128 Series Data Sheet, Rev. 1
140
Freescale Semiconductor
|
▷ |