MC9S08DZ128 Datasheet, PDF (151/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Central Processor Unit (S08CPUV5)
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode
where other serial background commands can be processed. This ensures that a host development system
can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop
mode. Refer to the Modes of Operation chapter for more details.
7.4.5 BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in
normal user programs because it forces the CPU to stop processing user instructions and enter the active
background mode. The only way to resume execution of the user program is through reset or by a host
debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug
interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the
BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background
mode rather than continuing the user program.
7.5 CALL and RTC Instructions
The CALL is similar to a jump-to-subroutine (JSR) instruction, but the subroutine that is called can be
located anywhere in the normal 64-Kbyte address space or on any page of program expansion memory.
When CALL is executed, a return address is calculated, then it and the current program page register value
are stacked, and a new instruction-supplied value is written to PPAGE. The PPAGE value controls which
of the possible 16-Kbyte pages is visible through the window in the 64-Kbyte memory map. Execution
continues at the address of the called subroutine.
The actual sequence of operations that occur during execution of CALL is:
1. CPU calculates the address of the next instruction after the CALL instruction (the return address)
and pushes this 16-bit value onto the stack, low byte first.
2. CPU reads the old PPAGE value and pushes it onto the stack.
3. CPU writes the new instruction-supplied page select value to PPAGE. This switches the destination
page into the program overlay window in the CPU address range 0x8000 0xBFFF.
4. Instruction queue is refilled starting from the destination address, and execution begins at the new
address.
This sequence of operations is an uninterruptable CPU instruction. There is no need to inhibit interrupts
during CALL execution. In addition, a CALL can be performed from any address in memory to any other
address. This is a big improvement over other bank-switching schemes, where the page switch operation
can be performed only by a program outside the overlay window.
For all practical purposes, the PPAGE value supplied by the instruction can be considered to be part of the
effective address. The new page value is provided by an immediate operand in the instruction.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
151