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MC9S08DZ128 Datasheet, PDF (133/458 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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6.5.9.3 Port J Pull Enable Register (PTJPE)
Chapter 6 Parallel Input/Output Control
R
W
Reset:
7
PTJPE7
0
6
PTJPE6
5
PTJPE5
4
PTJPE4
3
PTJPE3
2
PTJPE2
1
PTJPE1
0
0
0
0
0
0
Figure 6-54. Internal Pull Enable for Port J Register (PTJPE)
Table 6-52. PTJPE Register Field Descriptions
0
PTJPE0
0
Field
Description
7:0
PTJPE[7:0]
Internal Pull Enable for Port J Bits â Each of these control bits determines if the internal pull-up device is
enabled for the associated PTJ pin. For port J pins that are conï¬gured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port J bit n.
1 Internal pull-up device enabled for port J bit n.
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are conï¬gured.
6.5.9.4 Port J Slew Rate Enable Register (PTJSE)
R
W
Reset:
7
PTJSE7
0
6
PTJSE6
5
PTJSE5
4
PTJSE4
3
PTJSE3
2
PTJSE2
1
PTJSE1
0
0
0
0
0
0
Figure 6-55. Slew Rate Enable for Port J Register (PTJSE)
Table 6-53. PTJSE Register Field Descriptions
0
PTJSE0
0
Field
Description
7:0
PTJSE[7:0]
Output Slew Rate Enable for Port J Bits â Each of these control bits determines if the output slew rate control
is enabled for the associated PTJ pin. For port J pins that are conï¬gured as inputs, these bits have no effect.
0 Output slew rate control disabled for port J bit n.
1 Output slew rate control enabled for port J bit n.
Note: Slew rate reset default values may differ between engineering samples and ï¬nal production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
133
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