MC9S08DZ128 Datasheet, PDF (439/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
3 _{When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of fsys. After POR reset, the bus}
clock frequency changes to the untrimmed DCO frequency (f_reset = (f_{dco_ut})/4) because TRIM is reset to 0x80, FTRIM is reset
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.}
RESET PIN
t_extrst
Figure A-10. Reset Timing
BKGD/MS
RESET
t_MSSU
t_MSH
Figure A-11. Active Background Debug Mode Latch Timing
t_IHIL
PIAx/PIBx/PIDx/PIJx
Q/PIAx/PIBx/PIDx/PIJx
t_ILIH
Figure A-12. Pin Interrupt Timing
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
439