MC9S08DZ128 Datasheet, PDF (400/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Debug Module (S08DBGV3) (128K)
18.3.3.6 Debug Comparator C Low Register (DBGCCL)
Module Base + 0x0005
7
R
Bit 7
W
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
0
Bit 0
POR
or non-
0
0
0
0
0
0
0
0
end-run
Reset
end-run¹
U
U
U
U
U
U
U
U
Figure 18-7. Debug Comparator C Low Register (DBGCCL)
1 _{In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.}
Table 18-8. DBGCCL Field Descriptions
Field
Bits 7–0
Description
Comparator C Low Compare Bits — The Comparator C Low compare bits control whether Comparator C will
compare the address bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
18.3.3.7 Debug FIFO High Register (DBGFH)
Module Base + 0x0006
7
R Bit 15
6
Bit 14
5
Bit 13
4
Bit 12
3
Bit 11
2
Bit 10
1
Bit 9
0
Bit 8
W
POR
or non-
0
0
0
0
0
0
0
0
end-run
Reset
end-run¹
U
U
U
U
U
U
U
U
= Unimplemented or Reserved
Figure 18-8. Debug FIFO High Register (DBGFH)
1 _{In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.}
MC9S08DZ128 Series Data Sheet, Rev. 1
400
Freescale Semiconductor