MC9S08DZ128 Datasheet, PDF (407/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

18.3.3.14 Debug Trigger Register (DBGT)
Chapter 18 Debug Module (S08DBGV3) (128K)
Module Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
TRGSEL
W²
BEGIN
TRG
POR
or non-
0
1
0
0
0
0
0
0
end-run
Reset
end-run¹
U
U
0
0
U
U
U
U
= Unimplemented or Reserved
Figure 18-15. Debug Trigger Register (DBGT)
1 _{In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the control bits in this register do not change after reset.}
2 _{The DBG trigger register (DBGT) can not be changed unless ARM=0.}
Table 18-16. DBGT Field Descriptions
Field
Description
7
TRGSEL
6
BEGIN
3–0
TRG
Trigger Selection Bit — The TRGSEL bit controls the triggering condition for the comparators. See
Section 18.4.4, “Trigger Break Control (TBC)” for more information.
0 Trigger on any compare address access
1 Trigger if opcode at compare address is executed
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO.
0 Trigger at end of stored data
1 Trigger before storing data
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown in Table 18-17.
Table 18-17. Trigger Mode Encoding
TRG Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
Meaning
A Only
A Or B
A Then B
Event Only B
A Then Event Only B
A And B (Full Mode)
A And Not B (Full mode)
Inside Range
Outside Range
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
407