MC9S08DZ128 Datasheet, PDF (68/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Memory
Table 4-12 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (f_FCLK). The time for one cycle of FCLK is t_FCLK = 1/f_FCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where t_FCLK = 5 μs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-12. Program and Erase Times
Parameter
Byte program
Burst program
Sector erase
Mass erase
Sector erase abort
1 _{Excluding start/end overhead}
Cycles of FCLK
9
4
4000
20,000
4
Time if FCLK = 200 kHz
45 μs
20 μs¹
20 ms
100 ms
20 μs¹
4.6.3 Program and Erase Command Execution
The FCDIV register must be initialized after any reset and any error flag is cleared before beginning
command execution. The command execution steps are:
1. Write a data value to an address in the FLASH or EEPROM array. The address and data
information from this write is latched into the FLASH and EEPROM interface. This write is a
required first step in any command sequence. For erase and blank check commands, the value of
the data is not important. For sector erase commands, the address can be any address in the sector
of FLASH or EEPROM to be erased. For mass erase and blank check commands, the address can
be any address in the FLASH or EEPROM memory. FLASH and EEPROM erase independently
of each other.
NOTE
Before programming a particular byte in the FLASH or EEPROM, the
sector in which that particular byte resides must be erased by a mass or
sector erase operation. Reprogramming bits in an already programmed byte
without first performing an erase operation may disturb data stored in the
FLASH or EEPROM memory.
2. Write the command code for the desired command to FCMD. The six valid commands are blank
check (0x05), byte program (0x20), burst program (0x25), sector erase (0x40), mass erase (0x41),
and sector erase abort (0x47). The command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the
write to the memory array and before writing the 1 that clears FCBEF and launches the complete
command. Aborting a command in this way sets the FACCERR access error flag which must be
cleared before starting a new command.
MC9S08DZ128 Series Data Sheet, Rev. 1
68
Freescale Semiconductor