MC9S08DZ128 Datasheet, PDF (170/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
8.3 Register Definition
8.3.1 MCG Control Register 1 (MCGC1)
R
W
Reset:
7
6
CLKS
5
4
3
2
1
0
RDIV
IREFS IRCLKEN IREFSTEN
0
0
0
0
0
1
0
0
Figure 8-3. MCG Control Register 1 (MCGC1)
Table 8-1. MCG Control Register 1 Field Descriptions
Field
Description
7:6
CLKS
Clock Source Select — Selects the system clock source.
00 Encoding 0 — Output of FLL or PLL is selected.
01 Encoding 1 — Internal reference clock is selected.
10 Encoding 2 — External reference clock is selected.
11 Encoding 3 — Reserved, defaults to 00.
5:3
RDIV
External Reference Divider — Selects the amount to divide down the external reference clock. If the FLL is
selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected, the
resulting frequency must be in the range 1 MHz to 2 MHz. See Table 8-2 and Table 8-3 for the divide-by factors.
2
IREFS
Internal Reference Select — Selects the reference clock source.
1 Internal reference clock selected
0 External reference clock selected
1
Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK.
IRCLKEN 1 MCGIRCLK active
0 MCGIRCLK inactive
0
IREFSTEN
Internal Reference Stop Enable — Controls whether or not the internal reference clock remains enabled when
the MCG enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before
entering stop
0 Internal reference clock is disabled in stop
MC9S08DZ128 Series Data Sheet, Rev. 1
170
Freescale Semiconductor