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MC9S08DZ128 Datasheet, PDF (127/458 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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6.5.7.3 Port G Pull Enable Register (PTGPE)
Chapter 6 Parallel Input/Output Control
R
W
Reset:
7
PTGPE7
0
6
PTGPE6
5
PTGPE5
4
PTGPE4
3
PTGPE3
2
PTGPE2
1
PTGPE1
0
0
0
0
0
0
Figure 6-44. Internal Pull Enable for Port G Register (PTGPE)
Table 6-42. PTGPE Register Field Descriptions
0
PTGPE0
0
Field
Description
7:0
Internal Pull Enable for Port G Bits â Each of these control bits determines if the internal pull-up device is
PTGPE[7:0] enabled for the associated PTG pin. For port G pins that are conï¬gured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are conï¬gured.
6.5.7.4 Port G Slew Rate Enable Register (PTGSE)
R
W
Reset:
7
PTGSE7
0
6
PTGSE6
5
PTGSE5
4
PTGSE4
3
PTGSE3
2
PTGSE2
1
PTGSE1
0
0
0
0
0
0
Figure 6-45. Slew Rate Enable for Port G Register (PTGSE)
Table 6-43. PTGSE Register Field Descriptions
0
PTGSE0
0
Field
Description
7:0
Output Slew Rate Enable for Port G Bits â Each of these control bits determines if the output slew rate control
PTGSE[7:0] is enabled for the associated PTG pin. For port G pins that are conï¬gured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
Note: Slew rate reset default values may differ between engineering samples and ï¬nal production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
127
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